`timescale  1ns / 1ps

module tb_flash_rw;

// flash_rw Parameters
parameter real PERIOD  = 37;


// flash_rw Inputs
reg clk                            = 0 ;
reg rst_n                          = 0 ;
reg start                          = 0 ;

// flash_rw Outputs
wire led                            ;
wire done                           ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
end

flash_rw  u_flash_rw (
    .clk               (clk     ),
    .rst_n             (rst_n   ),
    .start             (start   ),

    .led               (led     ),
    .done              (done    )
);

initial
begin
    $dumpfile("tb_flash_rw.vcd");
    $dumpvars(0, tb_flash_rw);
    #(PERIOD*2) start = 1;
    #(PERIOD*2) start = 0;
    wait(done == 1'b1);
    $finish;
end

endmodule
